In the world of computers and processors there is an unrelenting drive for additional computing power and faster calculation times. In this context, then, systems in which several processors can be combined to work in parallel with one another are necessary.
Imaging systems which obtain visual images and perform various manipulations with respect to the data and then control the display of the imaged and stored data inherently require large amounts of computations and memory. Such imaging systems are prime candidates for multi-processing where different processors perform different tasks concurrently in parallel. These processors can be working together in the single instruction, multiple data mode (SIMD) where all of the processors are operating from the same instruction but obtaining data from various sources, or the processors can be working together in the multiple instruction, multiple data mode (MIMD) where each processor is working from a different set of instructions and working on data from different sources. For different operations, different configurations are necessary.
Some multi-processing systems are optimized for handling SIMD. In these systems all of the processors operate from a single instruction contained in a particular memory. In this situation, the system is set up to allow one memory to provide the instructions while the data is moved to and from other memories by processors assigned, at least for a period of time, to each other memory. In MIMD systems, each processor is typically assigned a particular memory for both instruction purposes and for data transfer.
One problem with attempts to run a multi-processing system that alternates between SIMD and MIMD modes is that vast amounts of switching, control and synchronism are required to allow for the vast number of permutations that can occur.
There is thus a need in the art for a system which handles a multi-processor having multi-memories such that the system can easily, on a cycle-by-cycle basis (if necessary) switch between the SIMD and MIMD modes on an interchangeable basis.
One method of solving the huge interconnection problem in complex systems such as the image processing system shown in one embodiment of the invention is to construct the entire processor as a single device. Conceptually this might appear easy to achieve, but in reality the problems are complicated.
First of all, an architecture must be created which allows for the efficient movement of information while at the same time conserving precious silicon chip space. The architecture must allow a very high degree of flexibility since once fabricated, it cannot easily be modified for different applications. Also, since the processing capability of the system will be high, there is a need for high band width in the movement of information on and off the chip. This is so since the physical number of leads which can attach to any one chip is limited.
It is also desirable to design an entire parallel processor system, such as an image processor, on a single silicon chip while maintaining the system flexible enough to satisfy wide ranging and constantly changing operational criteria.
It is further desirable to construct such a single chip parallel processor chip where the processor memory interface is easily adaptable to operation in various modes, such as SIMD and MIMD, as well as adaptable to efficient on-off chip data communications.